Two or more interconnected electronic systems (or subsystems) that transfer data from one system or subsystem to the other can have two clock domains (i.e., a first clock signal CLKA domain and a second clock signal CLKB domain) that operate at the same frequency (i.e., the signals CLKA and CLKB have a common base clock). However, the clock signals CLKA and CLKB do not necessarily operate in phase with each other and the data must be synchronized. Furthermore, since the clock signal CLKA is also gated via an enable signal, the clock signal CLKA is not toggling new data into the first system (or subsystem) for every cycle of the signal CLKA. The first system generates an indicator signal when data is ready for transfer to the second system. The second system (or subsystem) presents an indicator signal when data has been transferred from the first clock domain (the CLKA domain) to the second clock domain (the CLKB domain) and the transferred data is synchronized and ready for further processing.
One conventional method for providing the data transfer and the data ready indicator signals is via handshaking with request and acknowledge signals. The CLKA domain asserts the request signal. When the CLKB domain has received a valid data transfer, the CLKB domain asserts the acknowledge signal and the acknowledge signal clears the request signal in the CLKA domain. However, handshaking with request and acknowledge signals has tight timing constraints and is not conducive to static timing analysis (STA). Another disadvantage of such a method is that it reduces bandwidth and increases latency.
Another conventional method for providing the data transfer and the data ready indicator signals is to implement a common enable signal for both the CLKA and the CLKB domains. However, since the enable signal is generated external to the CLKA and CLKB domains, the timing of the enable signal is critical.
It would be desirable to have an architecture and/or method for implementing data transfer and data ready indicators from one clock domain to another clock domain that (i) reduces and/or eliminates timing criticality, and/or (ii) is conducive to static timing analysis.